Makefile basics

The basis of a simple Makefile

# Define source filename here:

SRC = main.cpp 

# Define output filename here:

OP = test.o

# Define compiler here:

CC = g++

# Define flags here:

CFLAGS = -o

program:

@echo "Building binary: "$(OP)

$(CC) $(CFLAGS) $(OP) $(SRC)

clean:

@echo "Removing binary:"$(OP)

rm $(OP)

The above example is the equivalent of;

g++ main.cpp -o test.o

Running the above with no argument - make will compile a source file (SRC) into an binary object file (OP).

Running make clean with  remove the binary object file (OP)

program: is the default, it will run when make is called with no arguments.

clean: will only run if make clean is called.

The @ suppresses outputting the command itself, so if we have;

echo "test"

This will output as follows:

echo "test"
test

Adding a @ to the beginning of the echo command;

@echo "test" will suppress outputting the command itself.

TBC